The present invention relates to an electric charge detector suitable for a solid-state image device. Particularly, the present invention relates to an electric charge detector that can reduce distributed noises to improve the SNR (Signal-to-Noise Ratio).
Conventionally, the solid-state image devices such as CCD solid-state image devices utilizing the charge transfer function include electric charge detectors respectively. The common floating diode amplifier-type electric charge detector is disclosed in, for example, the reference xe2x80x9cSOLID-STATE IMAGE DEVICESxe2x80x9d, authored by Yuji KIUCHI, supervised under Shin HASEGAWA, published by SHOKODO Publishing Co., and compiled by the Institute of Television Engineers of Japan (First Edition issued on Jul. 30, 1986), (see line 5, page 74 to line 5, page 75 and FIGS. 3.26(a) and 3.26(b)).
FIG. 7 is a plan view schematically illustrating the configuration of a conventional electric charge detector. FIG. 8 is a cross sectional view illustrating the configuration of the conventional electric charge detector, taken along the line Dxe2x80x94D of FIG. 7.
In the conventional electric charge detector, a P-type well region 29 is formed on the N-type semiconductor substrate 30. The P-type well region 29 is grounded. An N-type well region 22 is selectively formed on the P-well region 29. A LOCOS (local oxidation) structure (not shown), for instance, is formed around the N-type well region 22. Heavily-doped N-type diffused layers 26 and 28 are formed on the surface of the N-type well region 22.
A metal conductor (wire) 25 is in ohmic-contact with the heavily-doped N-type diffused layer 26. A source-follower amplifier 24 acting as an output amplifier is selectively connected to the metal conductor 25. An output circuit 24a is connected to the source follower amplifier 24 to receive the output signal VOUT.
An input gate electrode 21 is formed on the N-type well region 22 via the insulation film such as thermally-grown silicon dioxide film (not shown). The input gate electrode 21 controls the signal charge flown from an adjacent charge-coupled device (not shown). A gate terminal 21a is connected to the input gate electrode 21 to receive the gate electrode VOC.
A control terminal 28a is in connect with the surface of the heavily-doped N-type diffused layer 28 to reset potential VRD.
A gate electrode 27 is formed over the N-type well region 22 between the heavily-doped N-type diffused layers 26 and 28 via the insulation film (not shown) such as thermally-grown silicon dioxide. A gate terminal 27a is connected to the gate electrode 27 to receive the gate voltage xcfx86R.
In the conventional electric charge detector, a floating PN-junction diode 23 is formed of the P-type well region 29, the N-type well region 22, and the heavily-doped N-type diffused layer 26, which are disposed between the input gate electrode 21 and the input gate electrode 27. Moreover, a MOSFET-type reset transistor has the heavily-doped N-type diffused layer 26 acting as a source, the gate electrode 27 acting as a gate, and the heavily-doped N-type diffused layer 28 acting as a drain.
FIG. 9 is a timing chart illustrating the operation of the conventional electric charge detector. In the conventional electric charge detector, when the gate electrode 27 is set to a high level, the MOSFET-type reset transistor will be turned on, so that unwanted signal charges accumulated in the floating diode 23 is drawn to the heavily-doped N-type diffused region 28 acting as the drain thereof. At the same time, the surface potential of the floating diode 23 is held to a fixed reset potential VRD of about 12 to 15 volts.
Thereafter, when the gate electrode 27 is set to a low level, the reset transistor is turned off. In the charge-coupled device, the signal charge Q (that is, the signal current I (nA)) passes underneath the input gate electrode 21 and then sinks into the potential well of the floating diode 23. The signal charge Q is expressed by the following formula (1).
Q=∫Idtxe2x80x83xe2x80x83(1)
The source follower amplifier 24 outputs as an output signal VOUT the resulting variation of the channel potential of the floating diode 23 via the metal conductor 25. That is, the signal charge Q (expressed by the formula (1)) is converted into a variation in the surface potential of the floating diode 23. The source follower amplifier 24 amplifies the variation via the metal conductor 25 and then outputs it as a signal voltage.
When the output signal VOUT is output, the electric charge accumulated in the floating diode 23 are unwanted. This boosts the gate electrode 27 to a high level to reset the reset transistor 24. As a result, the unwanted charges are drawn out. The electric charges transferred from the charge-coupled device are sequentially detected by repeating the series of the operation, so that a predetermined voltage is obtained.
However, in the conventional electric charge detector, thermal noises and distributed noises generate because of the switching operation of the reset transistor in the reset operation, thus deteriorating the S/N ratio.
Those noises do not depend on the signal charge amount accumulated in the floating diode. Hence, this problem becomes remarkable as the integration density of the solid-state image device increases, that is, with shrinkage of the unit pixel size and reduction of a signal charge amount per pixel.
It is known that the thermal noise is proportional to the absolute temperature or the junction capacity of the floating diode. The floating diode is designed to reduce its size as small as possible, within an allowable range of the normal design rule.
The principle on the generation of distributed noises is disclosed in, for instance, xe2x80x9cPartition Noise in CCD Signal Detectionxe2x80x9d, written by N. Teranishi and N. Mutoh, IEEE Trans, Electron devices, Vol. ED-33, pp. 1696-1701(1986).
Each of FIGS. 10 to 12 is a schematic diagram illustrating the principle on generation of distributed noises according to steps. As shown in FIG. 10, the floating diode 23 accumulates electric charges. When the reset transistor is in an off state, the signal charges Q and electrons exist in the potential well of the floating diode 23.
Thereafter, as shown in FIG. 11, when the potential of the gate electrode 27 is in a high level and when the reset transistor is in an on state, the signal charge Q is drawn out of the potential well through the heavily-doped N-type diffused layer 28 acting as the drain of the reset transistor. In this case, electrons exist underneath the gate electrode 27 because the potential VRD of the reset channel underneath the gate electrode 27 is lower than that of the heavily-doped N-type diffused layer 28.
With the potential of the gate electrode 27 in a low level and with the reset transistor in an off state, as shown in FIG. 12, part of electrons existing in the reset channel are distributed to the floating diode. This causes the distributed noise. It is known that the charge amount q of the distributed noise is proportional to the reset channel capacity and the absolute temperature.
In consideration of variations in the channel potential of the reset transistor due to the device fabrication, the channel potential underneath the gate electrode 27 of the reset transistor is normally about 0.5 volts higher than the reset drain potential VRD at the on state.
The capacitance C1 of the reset channel is normally about xc2xc to ⅕ of that of the floating diode CO. Hence, the following formula (2) is applicable to the voltage conversion value Np of the distributed noise.
xe2x80x83C0xc3x97Np=C1xc3x970.5xc3x97K
C1=(xc2xc)C0xcx9c(⅕)C0xe2x80x83xe2x80x83(2)
where K is a ratio of electrons underneath the reset channel to be distributed to the floating diode 23 and is 0xe2x89xa6Kxe2x89xa61.
Therefore, the voltage conversion value Np of the distributed noise is expressed by the following formula:
Np=Kxc3x97(0.1xcx9c0.125)(V)xe2x80x83xe2x80x83(3)
In the normal situation where the potential of the reset channel is at a fixed value and there is no potential gradient between the reset drain and the floating diode, the distributed noise is split in half to the floating diode side and the reset drain side, that is, K is xc2xd. Hence, the voltage conversion value Np of a distributed noise is expressed by the formula (4).
Np=0.05xcx9c0.0625(V)xe2x80x83xe2x80x83(4)
The voltage conversion value Np is added as a dummy signal to the signal voltage.
Japanese Patent Publication No. 2828124 discloses the electric charge detector designed to reduce distributed noises. FIG. 13 is a cross sectional view schematically illustrating the conventional electric charge detector disclosed in Japanese Patent publication No. 2828124.
In the conventional electric charge detector, a P-type well region 39 is formed on the N-type semiconductor substrate 40. An N-type well region 32 is selectively formed on the P-type well region 39. A P-type diffused layer 36 is selectively formed on the surface of the N-type well region 32.
A reset transistor 34a, a load junction field-effect transistor (JFET) 34b, and an output circuit 35 are connected to the surface of the P-type well region 36.
An input gate electrode 31 is formed on the N-type well region 32 via the thermally-grown silicon oxide film (not shown) to control signal charges incoming from an adjacent charge coupled device (not shown). A gate electrode 31a is connected to the input gate electrode 31 to apply the gate voltage VOG. This conventional electric charge detector can suppress the electron distribution.
The above-mentioned electric charge detector can achieve the previously aimed results. However, the potential at the charge detection point F depends on the balance between the resistance rR of the reset transistor 34a, the on resistance rj of the load JFET 34b and the power source voltage (12 to 15 volts). Hence, this detector has the disadvantage in that the potential normally becomes a very low voltage, e.g. 9 to 10 volts, compared with the power source voltage.
With rR less than  less than rj, the potential at the point F is equal to the power source voltage. In this case, the drain potential of the load JFET 34b acting as a constant current source is substantially equal to the source potential thereof. For that reason, the load JFET 34b cannot sufficiently operate as a constant current source. FIG. 14A is a timing chart illustrating the output signal of the conventional electric charge detector. FIG. 14B is a timing chart illustrating the output signal of the conventional electric charge detector, with the potential at the point F equalized with the power source potential. When the potential at the point F is equal to the power source voltage, the waveform at the falling edge of the output signal is sloped, as shown in FIG. 14, thus decreasing the operational speed. The potential at the point F must be determined in design, by considering the characteristics of the load JFET 34b and the reset transistor 34a. However, such a design is very difficult because of variations in characteristic during the device fabrication.
The present invention is made to solve the above-mentioned problems.
Moreover, the objective of the invention is to provide an electric charge detector that can be easily designed and can prevent generation of distributed noises.
The objective of the present invention is achieved by a an electric charge detector comprising a semiconductor substrate; a first conductivity-type well region formed on the semiconductor substrate; a second conductivity-type well region formed on the first conductivity-type well region; potential-change detection means connected to the second conductivity-type well region, for detecting a change in a surface potential of the second conductivity-type well region; and a first conductivity-type diffused region formed on the surface of the second conductivity-type well region.
According to the present invention, when a floating diode formed of the second conductivity-type well region and the first conductivity-type diffused layer is forwardly biased, unwanted electric charges accumulated therein are ejected. The structure of the present invention requires no conventional MOS transistors, thus preventing the distributed noise of 0.05 to 0.0625 volts generated in the conventional device.
A floating diode may be formed of the first conductivity-type well region and the second conductivity-type well region.
Moreover, a forward bias potential can be applied to the diode formed of the first conductivity-type well region and the second conductivity-type well region to eject unwanted electric charges accumulated in the floating diode. The first conductivity-type well region may be grounded.
Moreover, according to the present invention, the electric charge detector further comprises an insulating film formed on the second conductivity-type well region; and gate electrodes formed on the insulating film, each for controlling electric charges entering from a charge-coupled device to the floating diode.
Moreover, according to the present invention, the electric charge detector further comprises a second conductivity-type diffused layer, acting as a connection region, formed in a surface of the second conductivity-type well region, the second conductivity-type diffused layer having an impurity concentration higher than that of the second conductivity-type well region, the connection region being connected to the potential-change detection region.